The Cranky Sysadmin

August 17, 2013

More Reverse Engineering of the Panologic Thin Client G1

Filed under: digital logic,Electronics,Pano Logic — Cranky Sysadmin @ 7:11 pm

I’ve been working on figuring out how to use my pano logic client as an FPGA dev board. Today I will detail the pin commections for the SPI flash, the Wolfson audio chip, and that partially identified Micron memory chip.
memory and audio details

July 21, 2013

Exploiting the FPGA in the Pano Logic Zero Client

Filed under: digital logic,Electronics,Pano Logic — Cranky Sysadmin @ 8:58 pm

I’ve managed to find some useful I/O and program the FPGA on my new (to me) Pano Logic Zero Clients. Below are the steps you could take to start working on these cheap but large FPGAs. I assume that you are facile with Xilinx ISE and have a jtag cable which works with either impact or adept2.
cheap FPGAs Woohoo

July 20, 2013

In Search of FPGAs or Pano Logic Generation 1 Teardown

Filed under: digital logic,Electronics,Pano Logic — Cranky Sysadmin @ 7:44 pm

In my general search for fpga’s and devices I might use for SDR projects, I came across a hackaday article on the topic. The comments on the topic are promising, so I went ahead and started looking for a Pano Logic Zero Client. I didn’t just find one. I found ten for $50 on ebay! These are the generation 1 version. It turns out that this is probably a better choice for me anyway. The generation 2 has an enormous Spartan-6 LX150 which is nice, but ISE webpack isn’t licensed to program it. The gen 1 has a Spartan 3E XC3S1600E. This is still a large (by my standards) fpga and the webpack license will program it fine. See below the fold for a teardown and some details.
The Fold

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