The Cranky Sysadmin A world of technology, fun, and ignorant rants.

July 21, 2013

Exploiting the FPGA in the Pano Logic Zero Client

Filed under: digital logic,Electronics,Pano Logic — Cranky Sysadmin @ 8:58 pm

I’ve managed to find some useful I/O and program the FPGA on my new (to me) Pano Logic Zero Clients. Below are the steps you could take to start working on these cheap but large FPGAs. I assume that you are facile with Xilinx ISE and have a jtag cable which works with either impact or adept2.

In my previous article, I described the pinout of the jtag port and I mentioned that J6 has a comment next to it, “Short to Program”. For my experiments just programming the FPGA directly, I don’t need to short J6. You’ll need to produce your own adapter from your jtag cable to match the one in the Pano Logic. After digging around at the easy things, like switches, LED’s, and the port labeled SPI, I found some nice IO that I can use for demonstration. I also found the global clock and an output from the programmable clock chip. I put these bits in a constraints file that looks like this:

#The clock is programable.
#NET LCLK LOC="J4" | IOSTANDARD = "LVCMOS33"; # lclk1
NET CLK LOC="U10" | IOSTANDARD = "LVCMOS33"; # gclk0

# These are exposed SPI pins, which are connected to the following pads.
NET "Led<0>"         LOC = "U3" | IOSTANDARD = "LVCMOS33";
NET "Led<1>"         LOC = "N10" | IOSTANDARD = "LVCMOS33";
NET "Led<2>"         LOC = "U16" | IOSTANDARD = "LVCMOS33";
NET "Led<3>"         LOC = "T4" | IOSTANDARD = "LVCMOS33";

# Built in LEDs. They're on the riser. Only two seem to be connected to
# fpga pins. I assume the third is network. These LEDs activate when the
# pins are low.
NET "Led<4>"         LOC = "H1" | IOSTANDARD = "LVCMOS33";
NET "Led<5>"         LOC = "L1" | IOSTANDARD = "LVCMOS33";

I then worked out a trivial test to ensure that I was able to program all of the LED’s and determine the clock speeds. Below is the verilog code for the test:


module pano_pins(
		 input wire clk,
		 output wire [5:0] Led
    );

   reg [30:0] 			   cntr;

   always @(posedge clk)
     cntr=cntr+1;

   assign Led = cntr [28:23];
   
endmodule

It’s just a counter which I borrow some bits from to set the LED’s. Because the built-in LED’s are active on low, the count looks a little funny. It all works ok. Below is some video proof. Forgive the lighting and quality. It was taken in a dark room with an iphone. I wanted to highlight the LED’s counting.

2 Comments »

  1. Hi,
    great work! How did you find the IOs and the clock? Did you just switch some IOs on and off to find the leds? I was thinking about trying the same with a Pano Logic G2.

    Comment by heye — July 29, 2013 @ 3:27 pm

  2. I found the clock by checking each potential pin listed in the data sheet (pin layout page). The first one I checked (labeled gclk0 in the datasheet) was the clock. I checked the rest of the potential clock pins and found one other (lclk1 in my .ucf file above). The method for “checking each pin” was to change the ucf entry for each potential clock pin, resynthesize, and download to the FPGA. This is clearly tedious and I suggest using ftjrev if you have a compatible usb serial converter.

    For I/O, I actually did a continuity check from the SPI pins to the BGA pins. If you look at the previous post, you’ll see that all of the pins are exposed through vias on the back, so it was a trivial but tedious process to find some IO.

    Comment by Cranky Sysadmin — August 2, 2013 @ 2:07 pm

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