The Cranky Sysadmin A world of technology, fun, and ignorant rants.

August 17, 2013

More Reverse Engineering of the Panologic Thin Client G1

Filed under: digital logic,Electronics,Pano Logic — Cranky Sysadmin @ 7:11 pm

I’ve been working on figuring out how to use my pano logic client as an FPGA dev board. Today I will detail the pin commections for the SPI flash, the Wolfson audio chip, and that partially identified Micron memory chip.

As an aside, that “program” jumper connects to PROG_B on the FPGA. I haven’t figured out how to use this yet.

I haven’t done any actual programming of these resources. You’ll have to look at a datasheet to see how to use them. I may have made mistakes, so don’t blame me if this information causes your Pano Logic to emit smoke or causes your cat to die.

I’ll start with the SPI memory since it’s easiest. If you look at a previous post, you’ll see that I hijacked the SPI plug pins to flash some LED’s. Well, it turns out that those are taken. They connect directly to the SPI chip as well as the FPGA. As you look at the board from the top, with the riser connector in the rear, pin 1 of the SPI connector is on the right. It’s labeled. Here is the table of connections.

SPI connector pin SPI chip pon FPGA pin function
1 4> Gnd
2 1 U3 S# (chip select)
3 2 N10 DQ1 (serial out)
4 6 U16 C (clock)
5 5 T4 DQ0 (serial in)
6 8 Vcc
3 W#
7 Hold#

The Wolfson audio chip has 10 pins that look interesting for control. I could only find 8 connections to the FPGA though. Below is the table of pins and functions.

Audio chip pin FPGA pin function
1 U9 MCLK
5 P10 BCLK
6 U15 DACDAT
7 N12 DACLRC
8 V3 ADCDAT
9 V15 ADCLRC
29 MODE
30 CSB
31 T3 SDIN
32 R10 SCLK

The bigish Micron memory chip took a while to nail down, and I still am not sure exactly which part it is, but it looks like Micron’s mobile low power DDR SDRAM. It’s a 90 ball chip, which seems to make it a 32 bit wide data bus. The data sheet in the intro is a 512MB part. This chip may or may not be that, but the pins seem close to correct so far. Below are the signal names and the FPGA pins that I’ve mapped. This process is tedious and I’m not done yet. I’ll update the page when I complete the pins.

signal name FPGA pin
A0 F11
A1 D13
A2 E13
A3 E11
A4 B16
A5 A16
A6 A12
A7 A11
A8 D14
A9 A14
A10 B14
A11 A13
A12
A13
CK J17
CK# J16
CKE E15
CS#
WE# P16
CAS# M14
RAS# H14
DM0 K12
DM1 K13
DM2 J14
DM3 H15
BA0 F12
BA1 E12

There are a lot of chips left to pin out. Of particular interest to me are the video DAC and the ethernet controller. As I said, this is a tedious process, so I don’t expect to be done quickly. If you’d like to contribute, I’ll be happy to attribute the work to you and post it here.

2 Comments »

  1. Hi Cranky :-)

    I’d be interested in getting involved with the reverse engineering effort, I have done some work on the G2, so I know what I am letting myself in for. G1 looks a bit simpler, and more accessible.

    If you are interested in selling me a spare G1, email me.

    Cheers

    Tim

    Comment by Tim — September 2, 2013 @ 9:51 am

  2. Did you ever get any more of the pins mapped?

    Also it seems it is a 512Mb part which is 64MB still plenty for implementing retro hardware etc.

    Comment by cb88 — April 29, 2015 @ 1:34 pm

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