The Cranky Sysadmin A world of technology, fun, and ignorant rants.

October 26, 2013

Pano Logic Updates from the UK

Filed under: digital logic,Electronics — Cranky Sysadmin @ 10:07 am

A few weeks ago, I shipped one of my pano-logic clients to a fellow in the UK named Tim. These neat devices are hard to get over there. Tim’s intent is to do further work figuring out how to utilize the FPGA and parts on the G1 client. I’m posting his latest update as a copy-and-paste from his email. I’ve formatted the links.

I have been making some progress with the Pano, so I thought I’d summarize what I have been up to. Apologies if there is some minor duplication in some areas.

1) Photos – I have taken some hi res photos: There are mirrored versions as well, as I find it useful to display the top and the mirrored bottom (or vice versa) next to each other. I’m also experimenting with Photoshopping to extract more specialist diagrams, like the via ones – I want to trace all the VIA connections, as I think this will be very useful when getting the peripherals to work.

2) Devices – Have identified some more devices – list attached. The memory is a MT46H8M32LF – this can be identified from the shortcode and this website:  Also identified the SOT-23’s – seem to be voltage regulators.

3) Connection Tracing – I use JTAG and the Universal Scan product for this – very useful, and reasonably quick. Set it to scan mode and then short vias with a suitable 3.3v source – note down which pin changes state. V crude, but workable. I attach the current list of connections I have identified. I should emphasize that this is a 1st draft, and very rough. Cannot explain why a lot of the SDRAM VIAs appear to have 2 FPGA connections. Dual port configuration? Fault in my technique? Don’t know yet. Also, I am testing with +3.3v – so won’t identify any pins that are currently 3.3v – need to retest the NC’s with a 0v probe.

4) Jig – I’ve built a jig to hold the board (photos in the Dropbox folder) – perhaps a bit over engineered, but I enjoyed doing it! Bought some pogo pins (awaiting delivery from Hong Kong) and the ultimate idea is to fashion a simple holder such that the pogo pin can be held against a VIA on the underside while probing devices on the top.

5) I have also posted a message or two on various Pano relevant threads – hopefully that will drive some traffic to your site, and hopefully they will be able to contribute.

(I attached the referenced spreadsheets below from Tim’s email)

xc3_pins ic_pins bom ic_pins xc3_pins


  1. Hi, thanks for your research into these boards. Helped me decide that I want to get some for myself :)

    Have you discovered anything new about these Pano logic boards? I’m getting a mix of gen-1 and gen-2 boxes in a while and might help a little with their research. Just want to make sure I won’t be doing something that’s already been done.

    Comment by Anonymous — July 23, 2015 @ 3:54 pm

  2. If you search for “Pano” on this blog, you should find all of the research I’ve done. The small amount of work I did was on the generation 1 version, which works with the free Xilinx tools. My understanding is that the FPGA on the second generation Pano is too big for the free tools.

    Comment by Cranky Sysadmin — July 31, 2015 @ 7:26 am

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